It is customary to call cache memory the memory built into the processor, which is characterized by high speed and is used to temporarily store the most frequently used data.
The need to use cache memory is explained by the difference in the speed of information exchange between the processor and various sections of the computer's memory. The work of any application begins by transferring the necessary data from a relatively slow hard disk into RAM (computer random access memory) into a dynamic random access section. From there, they can be transferred to the L2 cache (L2 memory) located in the processor chip or on a dedicated high-speed separate SRAM chip located next to the processor. Finally, the most used information can be transferred to the L1 cache (first level memory), which is a dedicated processor section. The size of the first level cache is only about 128 KB, the second level is already 512 KB. For comparison, the size of the RAM can be 1 GB. Execution of any command occurs according to a certain scheme: - analysis of data registers of information; - scanning of the data of the first level cache; - checking the information of the cache of the second level; - analyzing the data of the main memory; - access to the hard disk memory. The time spent by the processor to obtain the necessary data is in direct proportion to the place where the information is stored. Thus, access to the first level cache takes from 1 to 3 cycles, the second level - from six to twelve cycles, and to the main memory - tens, and in some cases - hundreds of cycles. The cache memory plays a special role in the process of server operation, because processor-to-memory traffic can be significant in these cases. The cache structure also serves the purpose of narrowing the gap between processor speeds, which are increasing by 50 percent annually, and RAM data rates, which are growing by only 5 percent. The ongoing development of the third and fourth levels of cache memory seems to be logical steps in this direction. Another possible direction of development may be the transition to programmatic management of cache memory.
